Stackable packages are currently a focus in the market of chip-packaging for packaging chips used in logic applications, mobile applications and consumer electronics. For such applications and consumer electronics, package-on-package (PoP) stacks are used so that packages can be tested before stacking. For embedded wafer level package technology (eWLP), e.g., embedded wafer level Ball grid array BGA (eWLB) technology, an embedded package-on-package (ePoP) version will be required in future. An ePoP may form the base package of the stack. Solder paste may be applied to a printed circuit board (PCB), and a bottom package, e.g. an embedded wafer level ball grid array, may be placed into the solder paste. Solder paste may be applied to the top of the ePOP. A standard BGA, e.g. a wire bonded or flip-chip BGA, or a wafer level ball grid array may be assembled on top of the ePoP package by placing the top package onto the ePOP. A reflow may then be carried out to attach the packages together. During the reflow the top package may then be connected to the bottom package.
The interconnection from a top package through an ePOP base or bottom package to the main board may be a vertical interconnection carried out in two different methods.
A first method makes use of via bars, using through-silicon via (TSV) technology or using PCB technology.
FIGS. 1A and 1B show how via bars may be used for providing a vertical interconnection from a top package to a bottom package. In this method, via bars 156, e.g. via bars comprising electrically conductive via connections, e.g. copper via connections from a package top 114 to bottom 112 side in a standard PCB board, may be placed into a package 102 prior to molding. Thus via bars 156 may already be pre-manufactured to establish a connection from the top 114 to the bottom 112 of package 102 even before a redistribution line is applied and may be pre-tested to guarantee a “known-good-via”. Each chip 106 may have one or more connection pads 108 formed at chip first side 120 here oriented to face the bottom 112 of package 102. The process is typically less flexible due to the pre-determined configuration of via bars 156.
Typically one, two or four via bars may be used for all interconnects, and smaller groups of via bars may not be possible. Moreover, via bars may be expensive. Silicon bars with TSVs or PCB bars may also be used, with PCB bars being the cheaper alternative to silicon bars. However, sufficiently high aspect ratio of via bars in this method may also be difficult to achieve as the via bars tend to be thick. The process has further difficulties because it relies on picking and placing the via bars in specific locations which may be difficult to control. The molding process is also difficult because via bar shifting during the molding process is very likely. Additional process steps for fixing the via bars may therefore be needed before the molding process.
After a mold material 110 is applied, top side 114 of package 102 may be ground to expose the interconnects. With reference to FIG. 1B, thin-film passivation layer 128, redistribution layer (RDL) 130 and solder stop layer 154 may be applied at chip first side 120 and/or package bottom side 112. Further thin-film passivation layer 140, further redistribution layer (RDL) 142 and further solder stop layer 144 may be applied to package top side 114. A solder ball 146 may be attached to redistribution layer 130 located on chip first side 120 and/or package bottom side 112. Due to the large dimensions of via bars, the process may result in a large package.
FIGS. 2A and 2B show illustrations of the use of via bars, e.g. conductive via bars, wherein the dimensions of exemplary via bars 262 are shown in μm. FIG. 2A shows two vias 256a, 256b comprising copper, each having a width of approximately maximally 150 μm formed adjacent each other. Each via may further comprise a hole plug material 258 which may have a width of approximately 125 μm. A Bismaleimide-Triazine epoxy (BT) or FR-4 polymer core area 260 may be the carrier material for the vias 256a, 256b. FIG. 2B shows a top-down view of via bar 262 having an array of vias 256 wherein the distance between each via may be approximately 175 to 200 μm.
In a second method, instead of using pre-fabricated via bars, prior to the mold-formation process, a etch process may be carried out to etch either through silicon to create a through silicon via (TSV) using a through-silicon via wet etch, or by laser drilling through the silicon or a mold component of the eWLB to create a through mold via (TMV) outside the chip. In the latter case, an overmolding process, i.e. forming a mold to isolate a chip may be carried out before the via etch and via fill processes. Both interconnect methods, TSV and TMV may be realized within the package area.
FIGS. 3A to 3D show the steps involved in TMV via creation such as by laser drilling in mold compounds. A chip 306 having one or more connection pads 308 at the first side 320 of chip 306 may be surrounded by a mold material 310, as shown in FIG. 3A. Via holes 338 may be drilled using a laser to create straight substantially vertical and parallel via holes 338, which may be formed substantially perpendicular to chip package bottom side 312 and top side 314, as shown in FIG. 3B. Via holes 338 may then be filled with a material 356 and further passivated, as shown in FIG. 3C. Chip package 302 may have a package bottom side 312 and package top side 314, as shown in FIG. 3D. Thin-film passivation layer 328, redistribution layer (RDL) 330 and solder stop layer 354 may be applied at the chip first side 320 and/or package bottom side 312. Further thin-film passivation layer 340, further redistribution layer (RDL) 342 and further solder stop layer 344 may be applied at package top side 314. Solder ball 346 may be attached to redistribution layer 330 located on the chip first side 320 and/or package bottom side 312, forming an embedded wafer level ball grid array package.
In the case wherein a TSV via may be created through silicon, it may be isolated, conductively filled and plugged. In comparison to the first method, the interconnection of the second method has higher flexibility. However, via drilling in a highly filled mold content is a difficult process. Filling the vias is very difficult due to the undercut and high filler content of the mold compound. Therefore, large via diameters may be needed due to the filler content in the mold compound. The process is slow and costly, and is not a typical thin-film processes and may not be available as part of standard fabrication technology. Therefore, yield may be low causing even properly functional devices to be scrapped, thus contributing to the cost and even exceeding the cost of scrapping the package slot, e.g. the package via. In comparison, the first method offers a relatively simple process and standard fabrication tools, e.g. equipment and processes are available and may be used. However, the process may be less flexible than the first method and the mold and mold frame may consume more space.
It is an aim to generate a cost effective three-dimensional interconnection from the base ePoP package to a device above the base ePOP package which alleviates the problems of via filling while creating the opportunity for a smaller chip package.